1. Technical Field of the Invention
The present invention relates in general to electronic memories and in particular to a segmented memory architecture and systems and methods using the same
2. Description of the Related Art
Dynamic random access memory (DRAM) is the dominant type of memory used in personal computers (PCs) and similar applications. Among other things, DRAM is relatively less expensive, consumes less power, and has a higher bit density when compared with other types of memory, such as SRAM (static random access memory). As a result, advances in DRAM technology have until recently been driven by the needs of the personal computer (PC) market.
Notwithstanding, networked systems, such as the Internet, are rapidly becoming equally important applications of DRAM and have thus begun to drive changes in DRAM technology. For instance, the data profile across a network is essentially of a random access nature as data are switched and routed between endpoints. Typically, SRAM is used in the routers and switches forming the network backbone to reduce access time and consequently achieve high data rates, however, as already noted, DRAM is less expensive and consumes considerably less power than SRAM, although DRAM has traditionally been much slower than SRAM. Hence, there has been considerable interest in improving DRAM random access cycle time such that DRAM can be successfully applied to network switches and routers.
Thus, a need for arisen for a high-speed, low-power and relatively inexpensive dynamic random access memory for switching applications. In particular, these low-power, high-speed memories should be suitable for use in the switching elements of networked and similar data transfer systems.
According to one embodiment of the inventive concepts, a memory is disclosed which includes a first memory segment comprising an array of rows and columns of memory cells, a selected column of cells in the first segment accessed through a dedicated sense amplifier associated with the first segment. A second memory segment comprises an array of rows and columns of memory cells, a selected column of cells in the second memory segment accessed through a dedicated sense amplifier associated with the second segment. A Read Input/Output line is coupled to the sense amplifier accessing the selected column of the first segment for reading data from the first segment during a selected access cycle. Additionally, a Write Input/Output line is coupled to the sense amplifier accessing the selected column of the second segment for simultaneously writing data to the second memory segment during the selected access cycle.
The inventive concepts allow for the construction and operation of dynamic random access memories with substantially reduced access times. These dynamic memories are particularly suited for use in switching memory applications, which are presently dominated by static random access memory technologies. Dynamic memories typically provide more bits per chip area, are less expensive and consume substantially less power than the static types.